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| NUS3046MN Overvoltage Protection IC with Integrated MOSFET This device represents a new level of safety and integration by combining the NCP346 overvoltage protection circuit (OVP) with a 30 V P-channel power MOSFET. This IC is specifically designed to protect sensitive electronic circuitry from overvoltage transients and power supply faults. During such hazardous events, the IC quickly disconnects the input supply from the load, thus protecting the load before any damage can occur. The OVP IC is optimized for applications that use an external AC-DC adapter or a car accessory charger to power a portable product or recharge its internal batteries. It has a nominal overvoltage threshold of 5.5 V which makes it ideal for single cell Li-Ion as well as 3/4 cell NiCD/NiMH applications. Features http://onsemi.com MARKING DIAGRAM 1 3046 AYWW G G 8 1 DFN8 CASE 506AL * * * * * * * * Overvoltage Turn-Off Time of Less Than 1.0 ms Accurate Voltage Threshold of 5.5 V, Nominal Control Input Compatible with 1.8 V Logic Levels -30 V Integrated P-Channel Power MOSFET Low RDS(on) = 66 mW @ -4.5 V Low Profile 3.3 x 3.3 mm DFN Package Suitable for Portable Applications Maximum Solder Reflow temperature @ 260C This is a Pb-Free Device 3046 = Device Code A = Assembly Location Y = Year WW = Work Week G = Pb-Free Package (Note: Microdot may be in either location) PIN ASSIGNMENT VCC OUT GATE SRC 8 7 6 5 9 10 GND 1 2 3 4 IN GND CNTRL DRAIN DRAIN Benefits * Provide Battery Protection * Integrated Solution Offers Cost and Space Savings * Integrated Solution Improves System Reliability Applications (Bottom View) ORDERING INFORMATION Device NUS3046MNT1G Package DFN8 (Pb-Free) Shipping 3000 Tape & Reel * Portable Computers and PDAs * Cell Phones and Handheld Products * Digital Cameras For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification Brochure, BRD8011/D. (c) Semiconductor Components Industries, LLC, 2006 June, 2006 - Rev. 1 Publication Order Number: NUS3046MN/D NUS3046MN Schottky Diode VCC SRC P-CH IN GATE + + - Vref NUS3046 GND CNTRL Microprocessor Port Logic FET Driver OUT C1 LOAD DRAIN AC/DC Adapter of Accessory Charger Figure 1. Simplified Schematic PIN FUNCTION DESCRIPTIONS Pin # 1 Symbol IN Pin Description This pin senses an external voltage point. If the voltage on this input rises above the overvoltage threshold (VTH), the OUT pin will be driven to within 1.0 V of VCC, thus disconnecting the P-channel power MOSFET. The nominal threshold level is 5.5 V and this threshold level can be increased with the addition of an external resistor between IN and VCC. Circuit Ground This logic signal is used to control the state of OUT and turn-on/off the P-channel power MOSFET. A logic High results in the OUT signal being driven to within 1.0 V of VCC which disconnects the FET. If this pin is not used, the input should be connected to ground. Drain pin of the P-channel power MOSFET Source pin of the P-channel power MOSFET Gate pin of the P-channel power MOSFET This signal drives the gate of a P-channel MOSFET. It is controlled by the voltage level on IN or the logic state of the CNTRL input. When an overvoltage event is detected, the OUT pin is driven to within 1.0 V of VCC in less than 1.0 msec provided that gate and stray capacitance is less than 12 nF. Positive Voltage supply. P-channel power MOSFET is guaranteed to be in ON state as long as VCC remains above 2.5 V and below the overvoltage threshold. 2, 10 3 GND CNTRL 4, 9 5 6 7 DRAIN SRC GATE OUT 8 VCC OVERVOLTAGE PROTECTION CIRCUIT TRUTH TABLE IN http://onsemi.com 2 NUS3046MN MAXIMUM RATINGS (TA = 25C unless otherwise stated) Rating OUT Voltage to GND Input and CNTRL Pin Voltage to GND VCC Maximum Range Maximum Power Dissipation (Note 1) Thermal Resistance Junction-to-Air (Note 1) OVP IC P-Channel FET Pin 7 1 3 8 - - Symbol VO Vinput VCNTRL VCC(max) PD RqJA Min -0.3 -0.3 -0.3 -0.3 - - - - -40 0 -65 2.5 Max 30 30 13 30 1.0 108.6 104.3 150 85 5.0 150 - -30 -20 20 -1.0 Unit V V V W C/W Junction Temperature Operating Ambient Temperature VCNTRL Operating Voltage Storage Temperature Range ESD Performance (HBM) (Note 2) Drain-to-Source Voltage Gate-to-Source Voltage Continuous Drain Current, Steady State, TA = 25C (Note 1) - - 3 - 1, 2, 3, 7, 8, 10 TJ TA - Tstg - VDSS VGS ID C C V C kV V V A Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 1. Surface-mounted on FR4 board using 1 inch sq pad size (Cu area = 1.127 in sq [1 oz] including traces). 2. Human body model (HBM): MIL STD 883C Method 3015-7, (R = 1500 W, C = 100 pF, F = 3 pulses delay 1 s). http://onsemi.com 3 NUS3046MN OVERVOLTAGE PROTECTION IC ELECTRICAL CHARACTERISTICS (TA= 25C, VCC = 6.0 V, unless otherwise specified) Characteristic VCC Operating Voltage Range Supply Current (ICC + IInput; VCC = 5.0 V Steady State) Input Threshold (VInput connected to VCC; VInput increasing) Input Hysteresis (VInput connected to VCC; VInput decreasing) Input Impedance (Input = VTh) CNTRL Voltage High (VCC = Vin = 4.0 V) CNTRL Voltage Low (VCC = Vin = 4.0 V) CNTRL Current High (VihCNTRL = 5.0 V, VCC = Vin = 5.0 V) CNTRL Current Low (VilCNTRL = 0.5 V, VCC = Vin = 5.0 V) Output Sink Current (VCC = Vin = 5.0 V; VOUT = 1.0 V) Output Voltage High (VCC = Vin = 5.0 V; CNTRL = 0 V, ISource = 10 mA) Output Voltage High (VCC = Vin = 5.0 V; CNTRL = 0 V, ISource = 0.25 mA) Output Voltage High (VCC = Vin = 5.0 V; CNTRL = 0 V, ISource = 0 mA) Output Voltage Low (VCC = Vin = 5.0 V; ISink = 0 mA; CNTRL = 0 V) Turn ON Delay - Input (Note 3) (VInput connected to VCC; VInput step down signal from 6.0 to 5.0 V; measured to 50% point of OUT) Turn OFF Delay - Input (VInput connected to VCC; CNTRL = 0 V; VInput stepup signal from 5.0 to 6.0 V; CL = 12 nF; Output > VCC - 1.0 V) Turn ON Delay - CNTRL (VCC = Vin = 5.0 V; CNTRL step down signal from 2.0 to 0.5 V; measured to 50% point of OUT) (Note 3) Turn OFF Delay - CNTRL (VCC = Vin = 5.0 V;CNTRL step up signal from 0.5 to 2.0 V; CL = 12 nF; Output > VCC -1.0 V) 3. Guaranteed by design. Symbol VCC(opt) Isupply VTh VHyst Rin Vih Vil Iih Iil ISink Voh Pin 8 1, 8 1 1 1 3 3 3 3 7 7 Min 2.5(+3) - 5.3 20 30 1.5 - - - 4 VCC - 1.0 VCC - 0.25 VCC - 0.1 - - Typ - 0.75 5.5 50 60 - - 95 10 10 - Max 25 1.2 5.7 200 100 - 0.5 200 20 16 - Unit V mA V mV kW V V mA mA mA V Vol TON IN 7 7 - 1.8 0.1 - V ms TOFF IN TON CT TOFF CT 7 7 7 - - - 0.5 10 0.6 1.0 - 1.0 ms ms ms P-CHANNEL MOSFET ELECTRICAL CHARACTERISTICS (TA= 25C unless otherwise specified) Parameter Drain to Source On Resistance VGS = -4.5 V, ID = -600 mA VGS = -4.5 V, ID = -1.0 A Zero Gate Voltage Drain Current VGS = 0 V, VDS = -24 V Turn On Delay (Note 4) VGS = -4.5 V, ID = -1.0 A, RG = 6.0 W, VDS = -15 V Turn Off Delay (Note 4) VGS = -4.5 V, ID = -1.0 A, RG = 6.0 W, VDS = -15 V Input Capacitance (Note 3) VGS = 0 V, f = 1.0 MHz, VDS = -15 V Gate to Source Leakage Current VGS = 20 V, VDS = 0 V Drain to Source Breakdown Voltage VGS = 0 V, ID = -250 mA Gate Threshold Voltage VGS = VDS, ID = -250 mA Symbol RDS(on) Min Typ 66 66 Max 110 110 -1.0 td(on) td(off) Cin IGSS V(BR)DSS V(GS)th 11 28 750 10 30 -3.0 -1.0 ns ns pF nA V V Units mW IDSS mA 4. Switching characteristics are independent of operating junction temperature. http://onsemi.com 4 NUS3046MN Normal Operation Figure 1 illustrates a typical configuration. The external adapter provides power to the protection system so the circuitry is only active when the adapter is connected. The OVP monitors the voltage from the charger and if the voltage exceeds the overvoltage threshold, Vth, the OUT signal drives the gate of the MOSFET to within 1.0 V of VCC, thus turning off the FET and disconnecting the source from the load. The nominal time it takes to drive the gate to this state is 400 nsec (1.0 msec maximum for gate capacitance of < 12 nF). The CNTRL input can be used to interrupt charging and allow the microcontroller to measure the cell voltage under a normal condition to get a more accurate measure of the battery voltage. Once the overvoltage is removed, the MOSFET will be turned on again. There are two events that will cause the OVP to turn off the MOSFET. * Voltage on IN Rises Above the Overvoltage Detection Threshold * CNTRL Input is Driven to a Logic HIGH Adjusting the Overvoltage Detection Point with External Resistors which equates to: VCC + Vx(1 ) R1 R2 ) R1 Rin) (eq. 2) So, as Rin approaches infinity: VCC + Vx(1 ) R1 R2) (eq. 3) This shows that Rin shifts the Vth detection point in accordance to the ratio of R1 / Rin. However, if R1 << Rin, this shift can be minimized. The following steps show this procedure. Designing around the Maximum Voltage Rating Requirements, V(VCC, IN) The maximum breakdown voltage between pins VCC and IN is 15 V. Therefore, care must be taken that the design does not exceed this voltage. Normally, the designer shorts VCC to IN, V(VCC, IN) is shorted to 0 V, so there is no issue. However, one must take care when adjusting the overvoltage threshold. In Figure 2, the R1 resistor of the voltage divider divides the V(VCC, IN) voltage to a given voltage threshold equal to: (VCC, IN) + VCC * (R1 (R1 ) (R2 Rin))) (eq. 4) The separate IN and VCC pins allow the user to adjust the overvoltage threshold, Vth, upwards by adding a resistor divider with the tap at the IN pin. However, the input impedance Rin does play a significant role in the calculation since it is several 10's of kW (Rin = 54 kW typical). The following equation shows the effects of Rin. VCC + Vx(1 ) R1 (R2 VCC V(VCC, IN) worst case equals 15 V, and VCC worst case equals 30 V, therefore, one must ensure that: R1 (R1 ) (R2 Rin)) t 0.5 (eq. 5) Rin)) (eq. 1) Where 0.5 = V(VCC, IN)max/VCCmax Therefore, the overvoltage threshold should be adjusted to voltage levels that are less than 15 V. If greater thresholds are desired, ON Semiconductor offers the NCP3045 which can withstand those voltages. R1 IN R2 Rin NUS3046 GND Figure 2. Voltage divider input to adjust overvoltage detection point http://onsemi.com 5 NUS3046MN Design Steps for Adjusting the Overvoltage Threshold 1..Use Typical Rin, and Vth Values from the Electrical Specifications 2..Minimize Rin Effect by Selecting R1 << Rin since: VOV + Vth(1 ) R1 R2 ) R1 Rin). (eq. 6) 3..Let X = Rin / R1 = 100. 4..Identify Required Nominal Overvoltage Threshold. 5..Calculate nominal R1 and R2 from Nominal Values: R1 + Rin X (eq. 7) R1 R2 + (VOV Vth * R1 Rin * 1) (eq. 8) The specification takes into account the hysteresis of the comparator, so the minimum input threshold voltage (Vth) is the falling voltage detection point and the maximum is the rising voltage detection point. One should design the input supply such that its maximum supply voltage in normal operation is less than the minimum desired overvoltage threshold. 8..Use worst case resistor tolerances to determine the maximum V(VCC,IN) V(VCC, IN) min + VCCmax * (R1min (R1min ) R2max)) (eq. 12) V(VCC, IN)typ + VCCmax * (R1typ (R1typ ) R2typ)) (eq. 13) V(VCC, IN) max + VCCmax * (R1max (R1max ) R2min)) (eq. 14) 6..Pick Standard Resistor Values as Close as Possible to these Values 7..Use min/max Data and Resistor Tolerances to Determine Overvoltage Detection Tolerance: VOVmin + Vthmin(1 ) R1min R2max ) R1min Rinmax) (eq. 9) VOVtyp + Vthtyp(1 ) R1typ R2typ ) R1typ Rintyp) (eq. 10) VOVmax + Vthmax(1 ) R1min R2max ) R1max Rinmin) (eq. 11) http://onsemi.com 6 NUS3046MN PACKAGE DIMENSIONS DFN8 CASE 506AL-01 ISSUE A D A B NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.25 AND 0.30mm. 4. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. DIM A A1 A3 b D D2 E E2 e K L MILLIMETERS MIN NOM MAX 0.80 0.90 1.00 0.00 0.03 0.05 0.20 REF 0.35 0.40 0.45 3.30 BSC 0.95 1.05 1.15 3.30 BSC 1.80 1.90 2.00 0.80 BSC 0.21 --- --- 0.30 0.40 0.50 PIN ONE REFERENCE E 2X 0.15 C 2X 0.15 C 0.10 C 8X 0.08 C D2 8X L 1 2X E2 2.95 8X K 8 5 8X b 0.10 C A B 0.05 C NOTE 3 1.20 2X BOTTOM VIEW 1.95 DIMENSIONS: MILLIMETERS *For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303-675-2175 or 800-344-3860 Toll Free USA/Canada Fax: 303-675-2176 or 800-344-3867 Toll Free USA/Canada Email: orderlit@onsemi.com N. American Technical Support: 800-282-9855 Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: 421 33 790 2910 Japan Customer Focus Center Phone: 81-3-5773-3850 ON Semiconductor Website: www.onsemi.com Order Literature: http://www.onsemi.com/orderlit For additional information, please contact your local Sales Representative http://onsemi.com 7 CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC EEEE EEEE EEEE 1 TOP VIEW (A3) A SIDE VIEW SEATING PLANE A1 D2 4 e C STYLE 1: PIN 1. IN 2. GND 3. CNTRL 4. DRAIN 5. SOURCE 6. GATE 7. OUT 8. VCC SOLDERING FOOTPRINT* 3.60 0.55 8X 0.45 0.80 PITCH 0.60 2X NUS3046MN/D |
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